FET Junction Temperature Monitoring Using Novel On-Chip Solution


A novel junction temperature monitoring sensor is proposed and experimentally demonstrated for application in MOS-gate power devices. The sensor is created using the polycide gate electrode layer of the devices to create a temperature-sensitive resistor without any additional fabrication steps. The resistor is located on the field oxide with one end grounded at the device reference terminal to isolate it from the device current and voltage transients. It allows in-situ monitoring of the device junction temperature during active circuit operation. The technology has been implemented to monitor the junction temperature of Silicon Carbide Junction Barrier Schottky Field Effect Transistors (SiC JBSFETs) with the bi-directional FET (BiDFET).

2024 IEEE Applied Power Electronics Conference and Exposition (APEC)
Ramandeep Narwal
Ramandeep Narwal
Ph.D. Candidate

Ramandeep Narwal is a Ph.D. candidate in the research group of Prof. Subhashish Bhattacharya at the FREEDM Systems Center, NC State University.